The application of high dose implant (to change resistance of an NFET or PFET) and high-k/metal gate stacks pose challenges to the existing processes of record for strip technologies, particularly for three dimensional (3D) finFet technologies with high aspect ratios. For example, current ashing processes have some epitaxial, high-k dielectric and workfunction metal damage concern.
More specifically, resist strip is required to minimize substrate surface oxidation/damage, and prevent the loss, redistribution and deactivation of implanted species in epi-Ge, high-k gate dielectric, workfunction metal and interlevel dielectric layers. Conventional methods of resist strip include plasma ashing approaches, which have limits that inhibit their ability to meet advanced strip requirements. For example, fluorine-containing chemistries are very effective for crust breakthrough and residue removal, but are known to produce substrate damage and dopant bleaching. On the other hand, oxidizing chemistries (e.g., O2/FG) are known to cause high substrate oxidation. Also, although forming gas (e.g., 96% N2+4% H2) by itself (without added oxygen) can achieve low substrate oxidation, these chemistries have been shown to cause issues with epitaxial erosion and TiN interaction with workfunction metals, high-dielectric materials and interlevel dielectric layers.
Another challenge includes unbalanced strip time (OE) when comparing open FET vs. non-open FET technologies. For example, ashing or stripping of optical planarization layers (OPL) or other polymer layers on a protected side of the device, e.g., PFET, can result in an added strip time. This added strip time results in the unwanted stripping or erosion of workfunction metals and high-dielectric materials. That is, such stripping or ashing processes causes high-k dielectric and workfunction metal damage due to the unbalanced strip time needed to remove remaining OPL on non-open area. This damage can contribute to especially large isolated device leakage (EG or eDRAM).